This invention relates generally to power regulation circuits and more particularly, it relates to a current-limiting circuit for use in a subscriber power controller device which supplies power across the S interface of the Integrated Services Digital Network (ISDN).
In the field of telecommunications, use of digital signalling techniques in transmitting information over long distances is gaining more and more prominence for a wide range of communication, including voice, computer data and video data. Typically, the S or subscriber lines interface as referred to by the Consultative Committee for Telegraphy and Telephony (CCITT) is used to interconnect ISDN terminal equipment to one or more network terminators such as private branch exchanges (PBX). A subscriber power controller (SPC) is used to convert the 40 volts delivered at the S interface into a stable, regulated 5 volt power supply for integrated circuits in the ISDN terminal equipment such as a telephone or data generating equipment. Such a power controller is manufactured and sold by Advanced Micro Devices, Inc., Sunnyvale, Calif., under part No. Am 7936. The subscriber power controller is an integrated circuit formed of a single-chip package and has as one of its capabilities a current-limiting feature which protect the device from damage caused by a short circuit at its output.
The subscriber power controller includes a control logic circuit which generates an output signal which sets the duty cycle of an output switching transistor. In other words, the output signal is pulse-width modulated. A current-limiting circuit of the present invention is provided as a part of the same subscriber power controller integrated circuit for performing such limiting of the current drawn from the output. The current-limiting circuit includes a comparator for comparing a voltage drop across an external resistor representative of the output current with a reference voltage. When the output current exceeds a certain limit, a current-limiting signal is fed to the control logic circuit for disabling or terminating of the output pulse on a pulse-by-pulse basis. Once the output current returns to its normal level, the output pulse will reappear at the very next cycle, thereby allowing for a short recovery time.